1. Field of the Invention
This invention relates to a drive device for a light emitting element array for use in the recording head of an image forming apparatus such as a copying apparatus or a printer, and particularly a light emitting element array having a self-scanning function.
2. Related Background Art
An example of a light emitting element array having a self-scanning function is described, in U.S. Pat. No. 5,451,977, Japanese Laid-Open Patent Application No. 1-238962, etc. This light emitting element array uses a light emitting thyristor as a basic element, and by effecting the coupling of the potential between the gates thereof, it has the shift register function of the light emission of the light emitting thyristor and effects self-scanning. By thus letting the light emitting element array itself have the self-scanning function, the compactness of the light emitting element array and the shorter pitch of the light emitting elements can be achieved, and the number of wires between the light emitting element array and a drive element for driving it can be greatly reduced.
FIG. 1 of the accompanying drawings is a diagram showing the equivalent circuit of such a light emitting element array having the self-scanning function. In FIG. 1, there is shown the circuit of a portion of the light emitting element array. In FIG. 1, reference characters S1-S4 designate switch elements for transfer (thyristors), and the anode terminal of each switch element is connected to a power source line V.sub.DD. The cathode terminals of odd number ones of the switch elements are connected to a clock line CL1 and the cathode terminals of even number ones of the switch elements are connected to a clock line CL2. A transfer clock .phi.1 for driving the switch elements is supplied to the clock line CL1 through a resistor R1, and a transfer clock .phi.2 is supplied to the clock line CL2. Reference characters D1-D3 denote diodes for coupling that are connected in series, and the gate terminals of corresponding switch elements are connected to the anode terminals of the respective diodes.
Also, resistors R.sub.G1 -R.sub.G3 are provided corresponding to the respective switch elements. One end of each resistor is connected to a power source V.sub.GA, and the other ends of the resistors are connected to the gate terminals of the corresponding switch elements. These switch elements for transfer, the diodes for coupling and the resistors together constitute a self-scanning circuit. Character .phi.S designates a start pulse for instructing to start transfer, and it is supplied to the gate terminal of the top switch element S1. Characters L1-L4 denote light emitting thyristors which are light emitting elements. The anode terminals of the light emitting thyristors are connected to the power source line V.sub.DD, the cathode terminals of the light emitting thyristors are connected to a clock line CLI, and the gate terminals of the light emitting thyristors are connected to the gate terminals of the corresponding switch elements. A drive signal .phi.1 for driving the light emitting thyristors is supplied to the clock line CLI through a resistor RI.
The operation of the above-described light emitting element array will now be described with reference to FIGS. 2A to 2D of the accompanying drawings. FIG. 2A shows the start pulse .phi.S, and the start pulse .phi.S of a high level is supplied to the anode terminal of the diode D1 when it instructs to start the operation. At the point of time whereat the start pulse .phi.S has been supplied, the transfer clocks .phi.1 and .phi.2 and the drive signal are at a high level (5V) and in this state, the cathode voltages of all switch elements and light emitting thyristors are nearly 5V and therefore, the switch elements and the light emitting thyristors are in their OFT state. Also, the start pulse .phi.S is at a high level and therefore, assuming that the forward drop voltage of the diodes is about 1V, the gate voltages of the switch elements become lower in succession due to the voltage drop of the diode for coupling in such a manner that the gate voltage of the top switch element S1 is 5V, the gate voltage of the next switch element S2 is 4V and the gate voltage of the next switch element S3 is 3V.
When thus in the high level state of the start pulse .phi.S, the transfer clock .phi.1 assumes a low level as shown in FIG. 2B, the switch element S1 of which the gate voltage is highest of the switch elements connected to the clock line CL1 assumes its ON state because the switch elements become ON when the cathode voltages thereof become lower, by diffusion potential V.sub.dif, than the gate voltages thereof. In this case, the cathode voltage of each switch element is substantially constant and therefore, the other switch elements connected to the clock line CL1 remain OFF. The gate voltage of the switch element S1 becomes nearly V.sub.DD. Also, when the switch element S1 becomes ON, the electric current thereof flows to the resistor R1, and since the cathode voltage of the switch element S1 at this time is substantially constant, the current value flowing to the switch element S1 is determined by the resistance value of the resistor R1.
When in the ON state of the switch element S, the drive signal .phi.1 assumes a low level as shown in FIG. 2D, the light emitting thyristor L1, of which the gate voltage is the highest of the light emitting thyristors connected to the clock line CLI becomes ON and emits light. The other light emitting thyristors, remain OFF. The electric current of the light emitting thyristor L1 flows to the resistor RI, and since at this time, the cathode voltage of the light emitting thyristor L1 is substantially constant, the current value of the light emitting thyristor L1 is determined by the resistance value of the resistor RI. Also, the emitted light intensity of the light emitting thyristor is determined by the electric current thereof.
When as shown in FIG. 2D, the drive signal .phi.I is brought to a high level after the light emitting thyristor L1 has emitted light for a predetermined time, the cathode voltage of the light emitting thyristor L1 becomes V.sub.DD and, therefore, the light emitting thyristor L1 becomes turned off. Next, as shown in FIG. 2C, the transfer clock .phi.2 is brought to a low level, the switch element S2, of which the gate voltage is the highest of the switch elements, connected to the clock line CL2 becomes ON, and the gate voltage thereof becomes nearly 5V. When in this state, as shown in FIG. 2B, the transfer clock .phi.1 is brought to a high level and as shown in FIG. 2A, the start pulse .phi.S is brought to a low level, the cathode voltage of the switch element S1 becomes V.sub.DD and this switch element becomes OFF, and the gate voltage thereof becomes 0V.
As a result of this, the ON state is transferred from the switch element S1 to the switch element S2, and the light emitting thyristor L2 is turned on by the next drive signal .phi.I and emits light for a predetermined time. In this manner, the switch element S1 is switched on by the start pulse .phi.S, and the switch elements in their ON state are transferred by 1 bit each by the transfer clocks .phi.1 and .phi.2. Along with it, the light emitting thyristors are successively shifted and the individual light emitting thyristors are driven in conformity with the drive signal, whereby the scanning of the light emitting thyristors which are light emitting elements is effected. Here, the transfer clocks .phi.1, .phi.2 and the drive signal .phi.I are applied through the resistors R1, R2 and RI, respectively, and the resistance values of the respective resistors are set so as to be optimum current values for the respective elements.
However, in the light emitting element array having the self-scanning function as described above, there is a range in the electric current of the switch elements within which normal transfer can be effected, and if the current value deviates from the range, the light emitting element array sometimes may not operate normally. Also, the light emitting element array has irregularity of manufacture and therefore, irregularity also occurs in the range of the electric current within which normal transfer is effected, depending on individual light emitting element arrays. In such a case, the range of the electric current for effecting the normal transfer of the switch elements is narrow and the driving condition is severe, and this has led to the problem that bad products are created due to the irregularity of manufacture of the light emitting element array, reducing the yield. Generally, when the light emitting element array is used in a recording head or the like, a plurality of light emitting element arrays are used while being connected in series on a substrate and therefore, if even one of them is bad, the substrate becomes a bad product (N.G.), and this has led to the problem that the cost of the apparatus is made remarkably high.
Also, when the light emitting element array of FIG. 1 is to be driven, a signal is supplied to the switch elements through the resistors R1 and R2 for limiting the electric current and therefore, if the resistors R1 and R2 are interchanged and adjusted so as to assume an optimum value in conformity with the irregularity of manufacture of the switch elements, much time is required for the selection and adjustment of the resistance values. This has led to the problem that the making of the apparatus is difficult. Further, in the prior art, the emitted light intensity of the light emitting thyristors is determined by the driving current and therefore, to record an image free of irregularity, it is necessary to suppress the irregularity of the driving current for the light emitting thyristors. However, the driving current for the light emitting thyristors is determined by characteristics such as the current and output resistance of the drive circuit itself or the resistor RI and therefore, to further improve the quality of image, it has been necessary to suppress the irregularity of these factors.